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? semiconductor components industries, llc, 2015 january, 2018 ? rev. 2 1 publication order number: fan53200/d fan53200 5 a, 2.4 mhz, digitally programmable tinybuck regulator descriptions the fan53200 is a step?down switching voltage regulator that delivers a digitally programmable output from an input voltage supply of 2.5 v to 5.5 v. the output voltage is programmed through an i 2 c interface capable of operating up to 3.4 mbps. using a proprietary architecture with synchronous rectification, the fan53200 is capable of delivering 5 a continuously at over 80% efficiency, while maintaining over 80% efficiency at load currents as low as 10 ma. the regulator operates at a nominal fixed frequency of 2.4 mhz, which reduces the value of the external components. additional output capacitance can be added to improve regulation during load transients without affecting stability. inductance up to 1.2 h may be used with additional output capacitance. at moderate and light loads, pulse frequency modulation (pfm) is used to operate in power?save mode with a typical quiescent current of 60 a. at higher loads, the system automatically switches to fixed?frequency control, operating at 2.4 mhz. in shutdown mode, the supply current drops to 0.1 a, reducing power consumption. pfm mode can be disabled if constant frequency is desired. the fan53200 is available in a 20?bump, 1.6 x 2.0 mm, wlcsp. features ? quiescent current in pfm mode: 60 a (typical) ? digitally programmable output voltage: ? 0.6 ?1.3875 v in 12.5 mv steps ? best?in?class load transient ? continuous output current capability: 5 a ? 2.5 v to 5.5 v input voltage range ? programmable slew rate for voltage transitions ? fixed?frequency operation: 2.4 mhz ? i 2 c?compatible interface up to 3.4 mbps ? internal soft?start ? input under?v oltage lockout (uvlo) ? thermal shutdown and overload protection ? 20?bump w afer?level chip scale package (wlcsp) applications ? graphic, and dsp processors arm , krait , omap , novathor , armada ? hard disk drives ? tablets, netbooks, ultra?mobile pcs ? smart phones ? gaming devices ordering information part number power?up defaults i 2 c slave address device id device marketing package vsel0 vsel1 fan53200uc35x off 1.15 v c0 0000 b9 wlcsp?20 FAN53200UC44X 1.15v 0.85 v c0 0000 cd wlcsp?20 www. onsemi.com wlcsp?20 case 567sh 1 figure 1. typical application sw c out l1 vin gnd vout c in agnd core processor (system load) gnd vdd vsel scl sda en fan53200
fan53200 www. onsemi.com 2 pin configuration figure 2. pin assignment (top view) table 1. pin descriptions pin # name description a1 vsel voltage select. when this pin is low, v out is set by the vsel0 register. when this pin is high, v out is set by the vsel1 register. a2 en enable. the device is in shutdown mode when this pin is low. all registers go to default values when en pin is low. a3 scl i 2 c serial clock a4 vout vout. sense pin for vout. connect to c out . b1 sda i 2 c serial data b2, b3, c1 ? c4 gnd ground. low?side mosfet is referenced to this pin. c in and c out should be returned with a minimal path to these pins. b4 agnd analog ground. all signals are referenced to this pin. avoid routing high dv/dt ac currents through this pin. d1, d2, e1, e2 vin power input voltage. connect to the input power source. connect to c in with minimal path. d3, d4, e3, e4 sw switching node. connect to the inductor.
fan53200 www. onsemi.com 3 table 2. absolute maximum ratings symbol parameter min max unit v in voltage on sw, vin pins ic not switching ?0.3 7.0 v ic switching ?0.3 6.5 voltage on all other pins ic not switching ?0.3 v in (note 1) v v out voltage on vout pin ?0.3 3.0 v v inov_slew maximum slew rate of v in > 6.5 v, pwm switching 100 v/ms esd electrostatic discharge protection level human body model per jesd22?a114 2000 v charged device model per jesd22?c101 1000 t j junction temperature ?40 +150 c t stg storage temperature ?65 +150 c t l lead soldering temperature, 10 seconds +260 c stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. 1. lesser of 7.0 v or v in + 0.3 v table 3. recommended operating conditions symbol parameter min typ max unit v in supply voltage range 2.5 5.5 v i out output current 0 5 a l inductor 0.33 h c in input capacitor 10 f c out output capacitor 44 f t a operating ambient temperature ?40 +85 c t j operating junction temperature ?40 +125 c product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. table 4. thermal properties symbol parameter min typ max unit ja junction?to?ambient thermal resistance (note 2) 38 c/w 2. see thermal considerations in the application information section.
fan53200 www. onsemi.com 4 table 5. electrical characteristics minimum and maximum values are at v in = 2.5 v to 5.5 v, t a = ?40 c to +85 c, unless otherwise noted. typical values are at t a = 25 c, v in = 5 v, and en = high. symbol parameter condition min typ max unit power supplies i q quiescent current i load = 0 60 a i sd h/w shutdown supply current en = gnd 0.1 5.0 a s/w shutdown supply current en = v in , buck_enx = 0 41 75 a v uvlo under?voltage lockout threshold v in rising 2.35 2.45 v v uvhyst under?voltage lockout hysteresis 350 mv en, vsel, sda, scl v ih high?level input voltage 1.1 v v il low?level input voltage 0.4 v v lhyst logic input hysteresis voltage 160 mv i in input bias current input tied to gnd or vin 0.01 1.00 a pgood i outl pgood pull?down current 1 ma i outh pgood high leakage current 0.01 1.00 a v out regulation v reg v out dc accuracy i out(dc) = 0, forced pwm, v out = vsel1 default value, 2.5 v v in 5.5 v ?1.5 1.5 % i out(dc) = 0 to 5 a, v out = vsel1, default value, auto pfm/pwm, 2.5 v v in 4.5 v ?2.0 4.0 % i out(dc) = 0 to 5 a, v out = vsel1, default value, auto pfm/pwm, 2.5 v v in 5.5 v ?3.0 5.0 % power switch and protection i limpk p?mos peak current limit open loop 6.3 7.4 8.5 a v sdwn input ovp shutdown rising threshold 6.15 v falling threshold 5.50 5.85 v frequency control f sw oscillator frequency 2.05 2.40 2.75 mhz r off vout pull?down resistance en = 0 or v in < v uvlo 160 product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. table 6. system characteristics symbol parameter min typ max unit v out_load load regulation i out = 1 a to 5 a 0.2 mv/a v out_line line regulation 3.6 v v in 4.0 v, i out = 3 a ?0.5 mv/v v out_ripple ripple voltage i out = 100 ma, pfm mode 16 mv i out = 2000 ma, pwm mode 3 efficiency v out = 1.15 v, i out = 100 ma 87 % v out = 1.15 v, i out = 500 ma 88 v out = 1.15 v, i out = 2 a 88 t ss soft?start en high to 95% of v out target (1.15 v) r load = 50 340 s v out_load_tran load transient i out = 0.1 a ? 1.2 a, t r = t f = 100 ns 20 mv v out_line_tran line transient v in = 3.0 v ? 3.6 v, t r = t f = 10 s, i out = 500 ma 20 mv note: the table above is verified by design and bench test while using the following external components: l = 0.33 h, dfe252012f?r33m (toko), c in = 10 f, c2012x5r1a106m (tdk), c out = 2 x 22 f, c2012x5r0j226m (tdk). these parameters are not tested in production. minimum and maximum values are at v in = 2.5 v to 5.5 v, v en = 1.8 v, t a = ?40 c to +85 c; circuit of figure 1, unless otherwise noted. typical values are at t a = 25 c, v in = 3.6 v, v out = 1.15 v, v en = 1.8 v, auto pfm mode.
fan53200 www. onsemi.com 5 typical characteristics unless otherwise specified, v in = 3.6 v, v out = 1.15 v, v en = 1.8 v, auto pfm mode, t a = 25 c; circuit and components according to figure 1. figure 3. efficiency vs. load current and input voltage figure 4. output regulation vs. load current and input voltage figure 5. output regulation vs. load current, over?temperature figure 6. pfm entry / exit level vs. input voltage figure 7. output ripple vs. load current figure 8. frequency vs. load current 74% 76% 78% 80% 82% 84% 86% 88% 90% 92% 94% 0 1000 2000 3000 4000 5000 load current (ma) 2.7 vin 3.6 vin 5.0 vin 0 5 10 15 20 25 0 1000 2000 3000 4000 5000 load current (ma) 2.7 vin 3.6 vin 5.0 vin 0 5 10 15 20 25 30 35 40 0 1000 2000 3000 4000 5000 load current (ma) ? 40c +25c +85c 200 400 600 800 1,000 1,200 2.5 3.0 3.5 4.0 4.5 5.0 5.5 input voltage (v) pfm exit pfm enter 0 5 10 15 20 25 0 1000 2000 3000 4000 5000 load current (ma) 3.6vin,auto 3.6vin,pwm 5.0vin,auto 5.0vin,pwm 0 500 1,000 1,500 2,000 2,500 3,000 0 1000 2000 3000 4000 5000 load current (ma) 3.6vin,auto 5.0vin,auto efficiency vout shift (mv) vout shift (mv) load current (ma) switching frequency (khz) output ripple (mvpp)
fan53200 www. onsemi.com 6 typical characteristics unless otherwise specified, v in = 3.6 v, v out = 1.15 v, v en = 1.8 v, auto pfm mode, t a = 25 c; circuit and components according to figure 1. figure 9. quiescent current vs. input voltage, over?temperature figure 10. shutdown current vs. input voltage, over?temperature figure 11. load transient, i out = 0.1 a 1.2 a, auto pfm mode, t r = t f = 100 ns figure 12. line transient, v in = 3.0 v 3.6 v, t r = t f = 10 s, i out = 500 ma figure 13. startup, r load = 50 20 30 40 50 60 70 80 2.5 3.0 3.5 4.0 4.5 5.0 5.5 input supply voltage (v) ? 40c +25c +85c 0 10 20 30 40 50 60 2.5 3.0 3.5 4.0 4.5 5.0 5.5 input voltage (v) en_buck=0, ? 40c en_buck=0, +25c en_buck=0, +85c en=0, +25c input supply current ( a) input current ( a)
fan53200 www. onsemi.com 7 operation description the fan53200 is a step?down switching voltage regulator that delivers a programmable output voltage from an input voltage supply of 2.5 v to 5.5 v. using a proprietary architecture with synchronous rectification, the fan53200 is capable of delivering 5 a at over 80% efficiency. the regulator operates at a nominal frequency of 2.4 mhz at full load, which reduces the value of the external components to 330 nh for the output inductor and 44 f for the output capacitor. high efficiency is maintained at light load with single?pulse pfm. the fan53200 integrates an i 2 c?compatible interface, allowing transfers up to 3.4 mbps. this communication interface can be used to: ? dynamically re?program the output voltage in 12.5 mv steps; ? reprogram the mode to enable or disable pfm; ? control voltage transition slew rate; or ? enable / disable the regulator. control scheme the fan53200 uses a proprietary non?linear, fixed? frequency pwm modulator to deliver a fast load transient response, while maintaining a constant switching frequency over a wide range of operating conditions. the regulator performance is independent of the output capacitor esr, allowing for the use of ceramic output capacitors. although this type of operation normally results in a switching frequency that varies with input voltage and load current, an internal frequency loop holds the switching frequency constant over a large range of input voltages and load currents. for very light loads, the fan53200 operates in discontinuous conduction mode (dcm) single?pulse pfm, which produces low output ripple compared with other pfm architectures. transition between pwm and pfm is relatively seamless, providing a smooth transition between dcm and continuous conduction mode (ccm). pfm can be disabled by programming the mode bit high in the vsel registers. enable and soft?start when the en pin is low; the ic is shut down, all internal circuits are off, and the part draws very little current. in this state, i 2 c cannot be written to or read from. all registers are reset to default values when en pin is low. when the output_discharge bit in the control register is enabled (logic high) and the en pin is low or the buck_enx bit is low, a load is connected from vout to gnd to discharge the output capacitors. raising en while the buck_enx bit is high activates the part and begins the soft?start cycle. during soft?start, the modulator?s internal reference is ramped slowly to minimize surge currents on the input and prevent overshoot of the output voltage. synchronous rectification is inhibited during soft?start, allowing the ic to start into a pre?charged capacitive load. if large output capacitance values are used, the regulator may fail to start. maximum c out capacitance for successfully starting with a heavy constant?current load is approximately: c outmax i limpk i load 320 v out (eq. 1) where c outmax is expressed in f and i load is the load current during soft?start, expressed in a. if the regulator is at its current limit for 16 consecutive current limit cycles, the regulator shuts down and enters tri?state before reattempting soft?start 1700 s later. this limits the duty cycle of full output current during soft?start to prevent excessive heating. the ic allows for software enable of the regulator, when en is high, through the buck_en bits. only buck_en1 is initialized high. table 7. hardware and software enable pins bits output voltage en vsel buck_en0 buck_en1 35x 44x 0 x x x off off 1 0 0 x 0 v 0 v 1 0 1 x 1.1 v 1.15 v 1 1 x 0 0 v 0 v 1 1 x 1 1.15 v 0.85 v vsel pin and i 2 c programming output voltage the output voltage is set by the nselx control bits in vsel0 and vsel1 registers. the output voltage is given as: v out 0.60 v nselx 12.5 mv (eq. 2) output voltage can also be controlled by toggling the vsel pin low or high. vsel low corresponds to vsel0 and vsel high corresponds to vsel1. upon por, vsel0 and vsel1 are reset to their default voltages, shown in table 11. transition slew rate limiting when transitioning from a low to high voltage, the ic can be programmed for one of eight possible slew rates using the slew bits in the control register (table 12). table 8. transition slew rate decimal bin slew rate 0 000 80 mv / s 1 001 40 mv / s 2 010 20 mv / s 3 011 10 mv / s 4 100 5 mv / s 5 101 2.5 mv / s 6 110 1.25 mv / s 7 111 0.625 mv / s
fan53200 www. onsemi.com 8 transitions from high to low voltage rely on the output load to discharge v out to the new set point. once the high?to?low transition begins, the ic stops switching until v out has reached the new set point. under?voltage lockout (uvlo) when en is high, the under?voltage lockout keeps the part from operating until the input supply voltage raises high enough to properly operate. this ensures proper operation of the regulator during startup or shutdown. input over?voltage protection (ovp) when v in exceeds v sdwn (about 6.2 v) the ic stops switching to protect the circuitry from internal spikes above 6.5 v. an internal filter prevents the circuit from shutting down due to noise spikes. current limiting a heavy load or short circuit on the output causes the current in the inductor to increase until a maximum current threshold is reached in the high?side switch. upon reaching this point, the high?side switch turns off, preventing high currents from causing damage. sixteen consecutive current limit cycles in current limit cause the regulator to shut down and stay off for about 1700 s before attempting a restart. thermal shutdown when the die temperature increases, due to a high load condition and/or high ambient temperature, the output switching is disabled until the die temperature falls sufficiently. the junction temperature at which the thermal shutdown activates is nominally 150 c with a 17 c hysteresis. i 2 c interface the fan53200?s serial interface is compatible with standard, fast, fast plus, and hs mode i 2 c?bus ? specifications. the f an53200?s scl line is an input and its sda line is a bi?directional open?drain output; it can only pull down the bus when active. the sda line only pulls low during data reads and when signaling ack. all data is shifted in msb (bit 7) first. i 2 c slave address in hex notation, the slave address assumes a 0 ls bit. the hex slave address is c0. table 9. i 2 c slave address hex bits 7 6 5 4 3 2 1 0 c0 1 1 0 0 0 0 0 r/w other slave addresses can be assigned. contact an on semiconductor representative. bus timing as shown in figure 14 , data is normally transferred when scl is low. data is clocked in on the rising edge of scl. typically, data transitions shortly at or after the falling edge of scl to allow ample time for the data to set up before the next scl rising edge. scl t su t h sda data change allowed figure 14. data transfer timing each bus transaction begins and ends with sda and scl high. a transaction begins with a st art condition, which is defined as sda transitioning from 1 to 0 with scl high, as shown in figure 15. scl t hd;sta sda slave address ms bit figure 15. start bit a transaction ends with a stop condition, which is defined as sda transitioning from 0 to 1 with scl high, as shown in figure 16. scl sda slave releases master drives ack(0) or nack(1) t hd;sto figure 16. stop bit during a read from the fan53200, the master issues a repeated start after sending the register address, and before resending the slave address. the repeated start is a 1 to 0 transition on sda while scl is high, as shown in figure 17. scl sda ack(0) or nack(1) slave releases sladdr ms bit t hd;sta t su;sta figure 17. repeated start timing high?speed (hs) mode the protocols for high?speed (hs), low?speed (ls), and fast?speed (fs) modes are identical, except the bus speed for hs mode is 3.4 mhz. hs mode is entered when the bus master sends the hs master code 00001xxx after a start condition. the master code is sent in fast or fast?plus mode (less than 1 mhz clock); slaves do not ack this transmission.
fan53200 www. onsemi.com 9 the master generates a repeated start condition that causes all slaves on the bus to switch to hs mode. the master then sends i 2 c packets, as described above, using the hs mode clock rate and timing. the bus remains in hs mode until a st op bit (figure 16) is sent by the master. while in hs mode, packets are separated by repeated start conditions (figure 17). read and write transactions the following figures outline the sequences for data read and write. bus control is signified by the shading of the packet, defined as ??????? ??????? master drives bus and slave drives bus all addresses and data are msb first. table 10. i 2 c bit definitions for figure 18 & figure 19 symbol definition s start, see figure 15 a ack. the slave drives sda to 0 to acknowledge the preceding packet. a nack. the slave sends a 1 to nack the preced- ing packet. r repeated start, see figure 17 p stop, see figure 16 s slave address a reg addr a a p 0 7 bits 8 bits 8 bits data 000 figure 18. write transaction s slave address a reg addr a 0 7 bits 8 bits r slave address 7 bits 1 a data a 8 bits 00 01 p figure 19. read transaction register description table 11. register map hex address name function 00 vsel0 controls v out settings when vsel pin = 0 01 vsel1 controls v out settings when vsel pin = 1 02 control determines whether v out output discharge is enabled and also the slew rate of positive transitions 03 id1 read?only register identifies vendor and chip type 04 id2 read?only register identifies die revision 05 monitor indicates device status
fan53200 www. onsemi.com 10 the following table defines the operation of each register bit. table 12. bit definitions bit name 35x 44x description vsel0 r/w register address: 00 7 buck_en0 0 1 software buck enable. when en pin is low, the regulator is off. when en pin is high, buck_en bit takes precedent. 6 mode0 0 0 0: allow auto pfm mode during light load . 1: forced pwm mode . 5:0 nsel0 101000 101100 sets v out value from 0.6v to 1.3875 v in 12.5 mv steps (see equation 2). vsel1 r/w register address: 01 7 buck_en1 1 1 software buck enable. when en pin is low, the regulator is off. when en pin is high, buck_en bit takes precedent. 6 mode1 0 0 0: allow auto pfm mode during light load. 1: forced pwm mode . 5:0 nsel1 101100 010100 sets v out value from 0.6v to 1.3875 v in 12.5 mv steps (see equation 2) . control r/w register address: 02 7 output_discharge 1 0 0: when the regulator is turned off, v out is not discharged. 1: when the regulator is turned off, v out discharges through an internal pull? down. 6:4 slew 000 000 sets the slew rate for positive voltage transitions (see table 8). 3 reserved 0 0 always reads back 0 2 reset reserved 0 0 1: reset all registers to default values. 0: always reads back 0 1:0 reserved 00 00 always reads back 00 id1 r register address: 03 7:5 vendor 100 signifies on semiconductor as the ic vendor 4 reserved 0 always reads back 0 3:0 die_id 0000 refer to ordering information id2 r register address: 04 7:4 reserved 0000 always reads back 0000 3:0 die_rev 0001 ic mask revision monitor r register address: 05 7 pgood 1 1: buck is enabled and soft?start is completed 6:0 not used 0000000 always reads back 000 0000
fan53200 www. onsemi.com 11 application information selecting the inductor the output inductor must meet both the required inductance and the energy?handling capability of the application. the inductor value affects the average current limit, the output voltage ripple, and the efficiency. the ripple current ( i) of the regulator is: i v out v in v in v out l f sw (eq. 3) the maximum average load current, i max(load), is related to the peak current limit, i lim(pk) by the ripple current such that: i max(load) i lim(pk) i 2 (eq. 4) the fan53200 is optimized for operation with l = 330 nh, but is stable with inductances up to 1.0 h (nominal). the inductor should be rated to maintain at least 80% of its value at i lim(pk) . failure to do so lowers the amount of dc current the ic can deliver. efficiency is af fected by the inductor dcr and inductance value. decreasing the inductor value for a given physical size typically decreases the dcr; but since i increases, the rms current increases, as do core and skin?effect losses. i rms i out(dc) 2 i 2 12 (eq. 5) the increased rms current produces higher losses through the r ds(on) of the ic mosfets as well as the inductor esr. increasing the inductor value produces lower rms currents, but degrades transient response. for a given physical inductor size, increased inductance usually results in an inductor with lower saturation current. table 13. effects of inductor value (from 330 nh recommended) on regulator performance i max(load) v out (equation 7) transient response increase decrease degraded inductor current rating the current limit circuit can allow substantial peak currents to flow through l1 under worst?case conditions. if it is possible for the load to draw such currents, the inductor should be capable of sustaining the current or failing in a safe manner. for space?constrained applications, a lower current rating for l1 can be used. the fan53200 may still protect these inductors in the event of a short circuit, but may not be able to protect the inductor from failure if the load is able to draw higher currents than the dc rating of the inductor. output capacitor and v out ripple table 14 suggests 0805 capacitors, but 0603 capacitors may be used if space is at a premium. due to voltage ef fects, the 0603 capacitors have a lower in?circuit capacitance than the 0805 package, which can degrade transient response and output ripple. increasing c out has negligible effect on loop stability and can be increased to reduce output voltage ripple or to improve transient response. output voltage ripple, v out , is calculated by: v out i l
f sw c out esr 2 2 d ( 1 d ) 1 8 f sw c out (eq. 6) where c out is the effective output capacitance. the capacitance of c out decreases at higher output voltages, which results in higher v out . equation 6 is only valid for continuous current mode (ccm) operation, which occurs when the regulator is in pwm mode. for large c out values, the regulator may fail to start under a load. if an inductor value greater than 1.0 h is used, at least 30 f of c out should be used to ensure stability. the lowest v out is obtained when the ic is in pwm mode and, therefore, operating at 2.4 mhz. in pfm mode, f sw is reduced, causing v out to increase. esl effects the equivalent series inductance (esl) of the output capacitor network should be kept low to minimize the square?wave component of output ripple that results from the division ratio c out esl and the output inductor (l out ). the square?wave component due to the esl can be estimated as: v out(sq) v in esl cout l1 (eq. 7) a good practice to minimize this ripple is to use multiple output capacitors to achieve the desired c out value. for example, to obtain c out = 20 f, a single 22 f 0805 would produce twice the square wave ripple as two x 10 f 0805. to minimize esl, try to use capacitors with the lowest ratio of length to width. 0805s have lower esl than 1206s. if low output ripple is a chief concern, some vendors produce 0508 or 0612 capacitors with ultra?low esl. placing additional small?value capacitors near the load also reduces the high?frequency ripple components. input capacitor the ceramic input capacitors should be placed as close as possible between the vin pin and pgnd to minimize the parasitic inductance. if a long wire is used to bring power to the ic, additional ?bulk? capacitance (electrolytic or tantalum) should be placed between c in and the power source lead to reduce under?damped ringing that can occur between the inductance of the power source leads and c in .
fan53200 www. onsemi.com 12 the effective c in capacitance value decreases as v in increases due to dc bias effects. this has no significant impact on regulator performance. thermal considerations heat is removed from the ic through the solder bumps to the pcb copper. the junction?to?ambient thermal resistance ( ja ) is largely a function of the pcb layout (size, copper weight, and trace width) and the temperature rise from junction to ambient ( t). for the fan53200uc, ja is 38 c/w when mounted on its four?layer evaluation board in still air with two?ounce outer layer copper weight and one?ounce inner layers. halving the copper thickness results in an increased ja of 48 c/w. for long?term reliable operation, the ic?s junction temperature (t j ) should be maintained below 125 c. to calculate maximum operating temperature (< 125 c) for a specific application: 1. use efficiency graphs to determine efficiency for the desired v in , v out , and load conditions. 2. calculate total power dissipation using: p t v out i load 1 1 (eq. 8) where is efficiency. estimate inductor copper losses using: p l i load 2 dcr l (eq. 9) 3. determine ic losses by removing inductor losses (step 3) from total dissipation: p ic p t p l (eq. 10) 4. determine device operating temperature: t p ic ja (eq. 11) and t ic t a t it is important to note that the r ds(on) of the ic?s power mosfets increases linearly with temperature at about 0.21%/ c. this causes the efficiency ( ) to degrade with increasing die temperature. recommended external components table 14. recommended capacitors component quantity vendor vendor c ( f) size rated c out 2 pieces c2012x5r0j226m tdk 22 0805 6.3 v c in 1 piece c2012x5r1a106m tdk 10 0805 10 v table 15. recommended inductors manufacturer part# l (nh) dcr (m ) i sat l w h toko dfe201612e?r47m 470 20 6.1 2.0 1.6 1.2 toko dfe252012f?r33m 330 14 8.5 2.5 2.0 1.2
fan53200 www. onsemi.com 13 layout recommendation figure 20. guidance for layer 1 figure 21. guidance for layer 2
fan53200 www. onsemi.com 14 figure 22. guidance for layer 3 figure 23. remote sensing schematic en sda scl vsel fan53200 vin vout sw gnd agnd gnd core processor (system load) l1 c in c out 3. the trace resistance between fan53200 and cpu should not exceed 30 m . this table provides resistance values for given copper oz 2. fb trace connects to ?+? side of cout near the load. 1. for remote sensing, additional output capacitors should be placed near the load. v do c out 4.9 2 500 25 6.5 1.5 500 25 9.7 1 500 25 19.4 0.5 500 25 resistance (m ) copper (oz) length (mils) width (mils) figure 24. remote sensing guidance, top layer
fan53200 www. onsemi.com 15 package dimensions wlcsp20 2.015x1.615x0.586 case 567sh issue o
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